Zur Hauptnavigation springen Direkt zum Inhalt springen

Logo: Deutsche Forschungsgemeinschaft (DFG) - zur Startseite Deutsche Forschungsgemeinschaft

Information für die Wissenschaft Nr. 64 | 16. November 2009
Priority Programme 1500 "Design and Architectures of Dependable Embedded Systems - A Grand Challenge in the Nano Age"

The Senate of the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) has announced the establishment of a new Priority Programme entitled "Design and Architectures of Dependable Embedded Systems - A Grand Challenge in the Nano Age". The programme is designed to run for six years.

For more than four decades the semiconductor industry complied to Moore's Law. However, the rapid pace of microminiaturisation (in the order of 1/2 25 since then) will soon approach its physical limits. When approaching these limits (where transistors are a mere few nanometer in size) various effects will be faced that jeopardise the reliable functionality of transistors and embedded systems in general. More specifically, the transistors' susceptibility against temperature and temperature variances, cosmic rays causing soft errors, tolerances of devices parameters during manufacturing and operation cause an increase and/or acceleration of permanent and transient faults and malfunction. Hence, the hardware of future embedded systems will be based upon and composed of unreliable components. This development mandates a paradigm shift whereas traditional design paradigms assumed a more or less fault-free hardware layer. Hence, we cannot any longer design embedded systems with this assumption.

It is therefore the goal of this Priority Programme to develop new methods and architectures that will - at system level - eliminate the negative effects (like malfunctioning, performance degradation, increased power consumption etc.) caused by the inherent unreliability observed at transistor and physical level. In essence, this programme is intended to conduct a paradigm shift: resiliency and self-adaptability should be deployed as means to cope with the inherent unreliability of future technology nodes as opposed to less efficient means like concurrency and simple flexibility used in the past. The meaning of adaptability in this context is, for instance, to reconfigure in order to attune to scenarios of unreliability. Resiliency in this context means to exhibit a certain degree of "immunisation" such that an adaption may not even be necessary. These radical new approaches will be pursued within this programme with the goal to ensure the economical profitability of nano-CMOS for some more decades.

This Priority Programme is based upon the following five columns to research the described problems:

  • Technology Abstraction: it denotes the interface to the actual physics and fabrication technology (which are not part of this programme) of the devices. Characterisation data of the physical and electronic layer needs to be made available at higher levels of the embedded system design process such that these can be included in their respective approaches to address the reliability problem.
  • Dependable Hardware Architectures: novel hardware architectures that incorporate the paradigms of self-adaptability and or resiliency shall be researched. Especially effects like susceptibility for stress, ambient conditions and manufacturing variability induced by Moore's Law shall be addressed through new mechanisms like, for instance, reconfiguration during run-time etc. Classical fault tolerance techniques and architecture shall not be deployed since they will not represent an efficient means to appropriately address these new challenges.
  • Dependable Embedded Software: new program paradigms for multi/many core architectures are required as far as they will exhibit robustness against the described scenarios. In order to achieve these goals the software must be hardware dependent such that the state of the underlying hardware can be reflected and faults can be compensated at various levels.
  • Design Methods: denotes the design flow comprising modelling, analysis, synthesis, simulation etc. at various levels of hardware and software abstraction. Thereby, the impact of unreliable devices shall be reflected within the design process and reliability shall be the most prominent design criteria. Stress factors (like system load, power densities, temperatures and ambient conditions) need to be involved in case they have an influence on the system's reliability.
  • Operation, Observation and Adaptation: these are cross topics of the whole Priority Programme and therefore they may be deployed at all abstraction layers and at any columns described above. Required are infrastructures for observation as well as mechanisms for adaptation in order to deploy means for fault recognition, fault avoidance and fault compensation with the goal to sustain a dependable operation.

Approaches within all five columns need always to take into consideration the entire system. Each project should make a contribution to at least one of the five columns "Technology Abstraction", "Dependable Hardware Architectures", "Dependable Embedded Software", "Design Methods", and "Operation, Observation and Adaptation" relevant to embedded systems. It needs to be clearly pointed out in how far the addressed unreliability scenarios are attributed to the migration to smaller device structures. Unreliability scenarios that origin from other sources (e.g. security scenarios) are not within the scope of this SPP. Furthermore, software-related approaches need to clearly show their hardware dependence. Dependability issues regarding distributed systems as well as purely device and technology-driven approaches are not within the scope of this SPP.

In order to achieve a high degree of multidisciplinarity, joint proposals are particularly welcome. Proposals for an initial two-year funding period should be submitted on paper and on CD-ROM (including the proposal and all appendices as pdf-files) no later than 19 February 2010. All proposals must be written in English. Submissions, marked as "SPP 1500 Design and Architectures of Dependable Embedded Systems", should be addressed to Deutsche Forschungsgemeinschaft, attn. Dr. Gerit Sonntag, 53170 Bonn, and, in addition, to Prof. Jörg Henkel, henkel@kit.edu. The first funding period is planned to start in October 2010.

Further Information

For scientific enquiries concerning the scope of the programme, please contact the Priority Programme's coordinator:

  • Prof. Dr. Jörg Henkel,
    Karlsruher Institut für Technologie (KIT),
    Institut für Technische Informatik,
    CES - Chair for Embedded Systems,
    Tel. +49 721 608-46050,

© 2010-2017 by DFG
Ausdruck aus dem Angebot der DFG (Deutsche Forschungsgemeinschaft)